Overview of Pentium Processors

Pentium® Processor Design Considerations


The Pentium processor at 100/133/166 MHz is a 3.3 V processor that operates at 100, 133 and 166 MHz core speeds (66 MHz external bus speeds). These processors are unified plane processors that use 3.3 V for all VCC pins.

The Pentium processor with MMX™ technology at 166/200 MHz is the newest addition to the embedded Pentium processor family. These processors provide several architectural enhancements. The internal data and code cache sizes have each been doubled from 8 Kbytes to 16 Kbytes, the branch prediction algorithm has been improved, and support for Intel MMX technology has been added. MMX technology is an extension to the Intel architecture (IA) instruction set that adds 57 new opcodes and a new MMX register set.

In the 80486 device, the cache was four-way set associative. The Pentium processors and Pentium processors with MMX technology are two-way set associative.

The Pentium processor with MMX technology operates at core frequencies of 166 and 200 MHz with a 66 MHz external bus. The Pentium processor with MMX technology uses 2.8 V for its internal core, while its peripheral I/O operates at 3.3 V (to provide full compatibility with existing chipset and SRAM). It is pin, package, and functionally compatible with the Pentium processor at 100/133/166 MHz and is operating system transparent.

Block Diagram - Renova




The introduction of high-performance Pentium processors into embedded designs enables new levels of system performance, but presents a new challenge: as processor performance increases, system performance bottlenecks can occur due to slow system buses. The PCI bus was introduced in Pentium processor-based systems to provide a high-speed communication path from the processor to other devices. The ISA bus remains to provide legacy support and is a low-cost solution for slower devices that do not require PCI performance.





DRAM Interface


The TXC implements a DRAM controller that supports a 64-bit memory array and main memory sizes from 4 Mbytes to 512 Mbytes (430HX) and 4 Mbytes to 256 Mbytes (430TX). The TXC generates all control signals (such as RAS#, CAS#, WE# using MWE#) and multiplexed addresses for the DRAM array. The address and data flows through the TXC for all DRAM accesses.

Seven Programmable Attribute Map (PAM) registers are used to specify cacheability, PCI enable, and read/write status of the memory space between 640 Kbytes and 1 Mbyte. Each PAM register defines a specific address area, enabling the system to selectively mark specific memory ranges as cacheable, read-only, write-only, read/write, or disabled. When a memory range is disabled, all CPU accesses to that range are automatically forwarded to the PCI bus. The TXC also supports one of two memory “holes”, either from 512 Kbytes to 640 Kbytes or from 15 Mbytes to 16 Mbytes in main memory. Accesses to the memory holes are forwarded to PCI.

The memory hole can be enabled/disabled through the DRAM Control register. All other memory from 1 Mbyte to 512 Mbytes is read/write and is cacheable. This is necessary to support some legacy applications that use memory I/O accesses, such as video capture devices that need fast memory I/O access.


Clock Generation

Clock generation and distribution is important in high-speed design. The skew between any two HCLK (Host clock) loads must be less than or equal to 1 ns. The skew between HCLK at the pin of the TXC and the pin of the CPU must be less than or equal to 0.3 ns. The skew between any two PCLK (PCI Clock, HCLK/2) loads must be less than or equal to 2 ns, the requirement of the PCI Rev 2.0 specification. For HCLK to PCLK ratios of 2-to-1, the rising edge of PCLKIN must be within 1 to 6 ns of the rising edge of HCLKIN, with HCLK leading PCLK.


PCI Bus

The PCI (Peripheral Component Interconnect) bus specification was developed to establish an industry standard, high-performance local bus architecture that is low-cost and allows product differentiation. It was first introduced in 1992. Revision 2.1 of the PCI Local Bus Specification has been available since June 1995.
With the PCI bus, devices that require fast access to system memory or to other devices can run at a high bus speed, up to 66 MHz. Also, with PCI system design, the PCI bus controller isolates other PCI devices from the processor host bus, preventing bus congestion and providing processor upgradability.